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» Memory Access Schemes for Configurable Processors
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HPCA
2002
IEEE
14 years 8 months ago
The Minimax Cache: An Energy-Efficient Framework for Media Processors
This work is based on our philosophy of providing interlayer system-level power awareness in computing systems [26, 27]. Here, we couple this approach with our vision of multipart...
Osman S. Unsal, Israel Koren, C. Mani Krishna, Csa...
TVLSI
2002
98views more  TVLSI 2002»
13 years 7 months ago
Minimizing memory access energy in embedded systems by selective instruction compression
We propose a technique for reducing the energy spent in the memory-processor interface of an embedded system during the execution of firmware code. The method is based on the idea ...
Luca Benini, Alberto Macii, Enrico Macii, Massimo ...
QEST
2007
IEEE
14 years 1 months ago
A Petri Net Model for Evaluating Packet Buffering Strategies in a Network Processor
Previous studies have shown that buffering packets in DRAM is a performance bottleneck. In order to understand the impediments in accessing the DRAM, we developed a detailed Petri...
Girish B. C., R. Govindarajan
IEEEPACT
1999
IEEE
13 years 12 months ago
Memory System Support for Image Processing
Image processing applications tend to access their data non-sequentially and reuse that data infrequently. As a result, they tend to perform poorly on conventional memory systems ...
Lixin Zhang, John B. Carter, Wilson C. Hsieh, Sall...
CSFW
2012
IEEE
11 years 10 months ago
Secure Compilation to Modern Processors
—We present a secure (fully abstract) compilation scheme to compile an object-based high-level language to lowchine code. Full abstraction is achieved by relying on a fine-grain...
Pieter Agten, Raoul Strackx, Bart Jacobs, Frank Pi...