117 search results - page 7 / 24 » Memory Access Schemes for Configurable Processors |
ICWS
2009
IEEE
14 years 4 months ago
2009
IEEE
The main memory management has been a critical issue to provide high performance in web cluster systems. To overcome the speed gap between processors and disks, many prefetch sche...
MICRO
1998
IEEE
13 years 12 months ago
1998
IEEE
This paper provides quantitative measurements of load latency tolerance in a dynamically scheduled processor. To determine the latency tolerance of each memory load operation, our...
LCPC
2007
Springer
14 years 1 months ago
2007
Springer
Recent studies have shown that programming in a Partition Global Address Space (PGAS) language can be more productive than programming in a message passing model. One reason for th...
SIAMCOMP
2000
13 years 7 months ago
2000
This paper describes a scheme to implement a shared address space of size m on an n-node mesh, with m polynomial in n, where each mesh node hosts a processor and a memory module. A...
ICCD
2006
IEEE
14 years 4 months ago
2006
IEEE
Pointer bugs associated with dynamically-allocated objects resulting in out-of-bounds memory access are an important class of software bugs. Because such bugs cannot be detected e...