167 search results - page 12 / 34 » Memory Arbitration and Cache Management in Stream-Based Syst... |
IEEEPACT
2009
IEEE
13 years 5 months ago
2009
IEEE
Abstract--Version management, one of the key design dimensions of Hardware Transactional Memory (HTM) systems, defines where and how transactional modifications are stored. Current...
SC
1992
ACM
13 years 12 months ago
1992
ACM
We are currently developing Willow, a shared-memory multiprocessor whose design provides system capacity and performance capable of supporting over a thousand commercial microproc...
ACMMSP
2006
ACM
14 years 1 months ago
2006
ACM
Stencil-based kernels constitute the core of many scientific applications on block-structured grids. Unfortunately, these codes achieve a low fraction of peak performance, due pr...
EUROMICRO
1999
IEEE
14 years 2 days ago
1999
IEEE
This research proposes a selective compressed memory system (SCMS) focusing on a compressed cache architecture, in which only data blocks with good compression efficiency are comp...
HPCA
2002
IEEE
14 years 8 months ago
2002
IEEE
This work is based on our philosophy of providing interlayer system-level power awareness in computing systems [26, 27]. Here, we couple this approach with our vision of multipart...