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CSREAESA
2003
13 years 9 months ago
Static Pattern Predictor (SPP) Based Low Power Instruction Cache Design
Energy dissipation in cache memories is becoming a major design issue in embedded microprocessors. Predictive filter cache based instruction cache hierarchy is effective in reduci...
Kugan Vivekanandarajah, Thambipillai Srikanthan, C...
KDD
2004
ACM
150views Data Mining» more  KDD 2004»
14 years 8 months ago
Complete This Puzzle: A Connectionist Approach to Accurate Web Recommendations Based on a Committee of Predictors
Abstract. We present a Context Ultra-Sensitive Approach based on two-step Recommender systems (CUSA-2step-Rec). Our approach relies on a committee of profile-specific neural networ...
Olfa Nasraoui, Mrudula Pavuluri
ISCA
1995
IEEE
109views Hardware» more  ISCA 1995»
13 years 11 months ago
Next Cache Line and Set Prediction
Accurate instruction fetch and branch prediction is increasingly important on today’s wide-issue architectures. Fetch prediction is the process of determining the next instructi...
Brad Calder, Dirk Grunwald
FPL
2006
Springer
125views Hardware» more  FPL 2006»
13 years 11 months ago
Application-Specific Memory Interleaving for FPGA-Based Grid Computations: A General Design Technique
Many compute-intensive applications generate single result values by accessing clusters of nearby points in grids of one, two, or more dimensions. Often, the performance of FGPA i...
Tom Van Court, Martin C. Herbordt
ISCA
2012
IEEE
260views Hardware» more  ISCA 2012»
11 years 10 months ago
A case for exploiting subarray-level parallelism (SALP) in DRAM
Modern DRAMs have multiple banks to serve multiple memory requests in parallel. However, when two requests go to the same bank, they have to be served serially, exacerbating the h...
Yoongu Kim, Vivek Seshadri, Donghyuk Lee, Jamie Li...