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MICRO
2010
IEEE
189views Hardware» more  MICRO 2010»
13 years 5 months ago
A Dynamically Adaptable Hardware Transactional Memory
Most Hardware Transactional Memory (HTM) implementations choose fixed version and conflict management policies at design time. While eager HTM systems store transactional state in-...
Marc Lupon, Grigorios Magklis, Antonio Gonzá...
MICRO
2003
IEEE
96views Hardware» more  MICRO 2003»
14 years 1 months ago
Scalable Hardware Memory Disambiguation for High ILP Processors
This paper describes several methods for improving the scalability of memory disambiguation hardware for future high ILP processors. As the number of in-flight instructions grows...
Simha Sethumadhavan, Rajagopalan Desikan, Doug Bur...
MLDM
2009
Springer
14 years 2 months ago
Memory-Based Modeling of Seasonality for Prediction of Climatic Time Series
The paper describes a method for predicting climate time series that consist of significant annual and diurnal seasonal components and a short-term stockastic component. A memory...
Daniel Nikovski, Ganesan Ramachandran
ICCD
2004
IEEE
129views Hardware» more  ICCD 2004»
14 years 4 months ago
Cache Array Architecture Optimization at Deep Submicron Technologies
A cache access time model, PRACTICS (PRedictor of Access and Cycle TIme for Cache Stack), has been developed to optimize the memory array architecture for the minimum access and c...
Annie (Yujuan) Zeng, Kenneth Rose, Ronald J. Gutma...
SAMOS
2007
Springer
14 years 1 months ago
The Weight-Watcher Service and its Lightweight Implementation
—This paper presents the Weight-Watcher service. This service aims at providing resource consumption measurements and estimations for software executing on resourceconstrained de...
Benoît Garbinato, Rachid Guerraoui, Jarle Hu...