Sciweavers

236 search results - page 36 / 48
» Memory Bank Predictors
Sort
View
ASPDAC
2006
ACM
178views Hardware» more  ASPDAC 2006»
14 years 1 months ago
Hardware architecture design of an H.264/AVC video codec
Abstract—H.264/AVC is the latest video coding standard. It significantly outperforms the previous video coding standards, but the extraordinary huge computation complexity and m...
Tung-Chien Chen, Chung-Jr Lian, Liang-Gee Chen
ASPLOS
2004
ACM
14 years 1 months ago
Scalable selective re-execution for EDGE architectures
Pipeline flushes are becoming increasingly expensive in modern microprocessors with large instruction windows and deep pipelines. Selective re-execution is a technique that can r...
Rajagopalan Desikan, Simha Sethumadhavan, Doug Bur...
IAJIT
2010
150views more  IAJIT 2010»
13 years 6 months ago
Optimal DSP Based Integer Motion Estimation Implementation for H.264/AVC Baseline Encoder
: The coding gain of the H.264/AVC video encoder mainly comes from the new incorporated prediction tools. However, their enormous computation and ultrahigh memory bandwidth are the...
Imen Werda, Haithem Chaouch, Amine Samet, Mohamed ...
HPCA
2002
IEEE
14 years 8 months ago
Evaluation of a Multithreaded Architecture for Cellular Computing
Cyclops is a new architecture for high performance parallel computers being developed at the IBM T. J. Watson Research Center. The basic cell of this architecture is a single-chip...
Calin Cascaval, José G. Castaños, Lu...
ISCA
2000
IEEE
121views Hardware» more  ISCA 2000»
14 years 5 days ago
Selective, accurate, and timely self-invalidation using last-touch prediction
Communication in cache-coherent distributed shared memory (DSM) often requires invalidating (or writing back) cached copies of a memory block, incurring high overheads. This paper...
An-Chow Lai, Babak Falsafi