236 search results - page 4 / 48 » Memory Bank Predictors |
ISCA
1999
IEEE
14 years 5 days ago
1999
IEEE
Recent research advocates using general message predictors to learn and predict the coherence activity in distributed shared memory (DSM). By accurately predicting a message and t...
ISCAS
2003
IEEE
14 years 1 months ago
2003
IEEE
To increase the bandwidth of synchronous memories that are widely adopted for high performance memory systems, a predictive mode control scheme is proposed to reduce memory latenc...
EUROPAR
2009
Springer
14 years 15 days ago
2009
Springer
In response to the constant increase in wire delays, Non-Uniform Cache Architecture (NUCA) has been introduced as an effective memory model for dealing with growing memory latenci...
ICASSP
2008
IEEE
14 years 2 months ago
2008
IEEE
Multiple memory banks design is employed in many high performance DSP processors. This architectural feature supports higher memory bandwidth by allowing multiple data memory acce...
MICRO
2009
IEEE
14 years 2 months ago
2009
IEEE
DRAM systems achieve high performance when all DRAM banks are busy servicing useful memory requests. The degree to which DRAM banks are busy is called DRAM Bank-Level Parallelism ...