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SAC
2008
ACM
13 years 7 months ago
Exploiting program cyclic behavior to reduce memory latency in embedded processors
In this work we modify the conventional row buffer allocation mechanism used in DDR2 SDRAM banks to improve average memory latency and overall processor performance. Our method as...
Ehsan Atoofian, Amirali Baniasadi
ISPASS
2003
IEEE
14 years 1 months ago
Memory reference reuse latency: Accelerated warmup for sampled microarchitecture simulation
Abstract— This paper proposes to speedup sampled microprocessor simulations by reducing warmup times without sacrificing simulation accuracy. It exploiting the observation that ...
John W. Haskins Jr., Kevin Skadron
ICML
1997
IEEE
14 years 8 months ago
Predicting Multiprocessor Memory Access Patterns with Learning Models
Machine learning techniques are applicable to computer system optimization. We show that shared memory multiprocessors can successfully utilize machine learning algorithms for mem...
M. F. Sakr, Steven P. Levitan, Donald M. Chiarulli...
IJCNN
2006
IEEE
14 years 1 months ago
Sparse Bayesian Models: Bankruptcy-Predictors of Choice?
Abstract— Making inferences and choosing appropriate responses based on incomplete, uncertainty and noisy data is challenging in financial settings particularly in bankruptcy de...
Bernardete Ribeiro, Armando Vieira, João Ca...
DAC
2002
ACM
14 years 8 months ago
Automatic data migration for reducing energy consumption in multi-bank memory systems
An architectural solution to reducing memory energy consumption is to adopt a multi-bank memory system instead of a monolithic (single-bank) memory system. Some recent multi-bank ...
Victor De La Luz, Mahmut T. Kandemir, Ibrahim Kolc...