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» Memory Exploration for Low Power, Embedded Systems
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ISCA
2009
IEEE
189views Hardware» more  ISCA 2009»
14 years 2 months ago
Hybrid cache architecture with disparate memory technologies
Caching techniques have been an efficient mechanism for mitigating the effects of the processor-memory speed gap. Traditional multi-level SRAM-based cache hierarchies, especially...
Xiaoxia Wu, Jian Li, Lixin Zhang, Evan Speight, Ra...
FPL
2006
Springer
242views Hardware» more  FPL 2006»
13 years 11 months ago
TMD-MPI: An MPI Implementation for Multiple Processors Across Multiple FPGAs
With current FPGAs, designers can now instantiate several embedded processors, memory units, and a wide variety of IP blocks to build a single-chip, high-performance multiprocesso...
Manuel Saldaña, Paul Chow
CODES
2009
IEEE
14 years 2 months ago
A standby-sparing technique with low energy-overhead for fault-tolerant hard real-time systems
Time redundancy (rollback-recovery) and hardware redundancy are commonly used in real-time systems to achieve fault tolerance. From an energy consumption point of view, time redun...
Alireza Ejlali, Bashir M. Al-Hashimi, Petru Eles
DATE
2004
IEEE
126views Hardware» more  DATE 2004»
13 years 11 months ago
GRAAL - A Development Framework for Embedded Graphics Accelerators
This paper presents a versatile hardware/software cosimulation and co-design environment for embedded 3D graphics accelerators. The GRAphics AcceLerator design exploration framewo...
Dan Crisu, Sorin Cotofana, Stamatis Vassiliadis, P...
CODES
2009
IEEE
14 years 2 months ago
FRA: a flash-aware redundancy array of flash storage devices
Since flash memory has many attractive characteristics such as high performance, non-volatility, low power consumption and shock resistance, it has been widely used as storage med...
Yangsup Lee, Sanghyuk Jung, Yong Ho Song