89 search results - page 4 / 18 » Memory Hierarchy Design for a Multiprocessor Look-up Engine |
HIPEAC
2011
Springer
12 years 8 months ago
2011
Springer
In chip multiprocessors (CMPs), data accesslatency dependson the memory hierarchy organization, the on-chip interconnect (NoC), and the running workload. Reducing data access late...
ISCA
1996
IEEE
14 years 21 days ago
1996
IEEE
In the future, advanced integrated circuit processing and packaging technology will allow for several design options for multiprocessor microprocessors. In this paper we consider ...
HPCA
1998
IEEE
14 years 24 days ago
1998
IEEE
Run-time parallelization is often the only way to execute the code in parallel when data dependence information is incomplete at compile time. This situation is common in many imp...
CGO
2003
IEEE
14 years 5 days ago
2003
IEEE
In this paper, we present METRIC, an environment for determining memory inefficiencies by examining data traces. METRIC is designed to alter the performance behavior of applicatio...
PLDI
2012
ACM
11 years 11 months ago
2012
ACM
While graphics processing units (GPUs) provide low-cost and efficient platforms for accelerating high performance computations, the tedious process of performance tuning required...