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ARCS
2010
Springer
14 years 3 months ago
How to Enhance a Superscalar Processor to Provide Hard Real-Time Capable In-Order SMT
This paper describes how a superscalar in-order processor must be modified to support Simultaneous Multithreading (SMT) such that time-predictability is preserved for hard real-ti...
Jörg Mische, Irakli Guliashvili, Sascha Uhrig...
DATE
2002
IEEE
94views Hardware» more  DATE 2002»
14 years 1 months ago
A Powerful System Design Methodology Combining OCAPI and Handel-C for Concept Engineering
In this paper, we present an efficient methodology to validate high performance algorithms and prototype them using reconfigurable hardware. We follow a strict topdown Hardware/So...
Klaus Buchenrieder, Andreas Pyttel, Alexander Sedl...
CCGRID
2010
IEEE
13 years 7 months ago
An Adaptive Data Prefetcher for High-Performance Processors
—While computing speed continues increasing rapidly, data-access technology is lagging behind. Data-access delay, not the processor speed, becomes the leading performance bottlen...
Yong Chen, Huaiyu Zhu, Xian-He Sun
DAC
1997
ACM
14 years 4 days ago
Formal Verification of a Superscalar Execution Unit
Abstract. Many modern systems are designed as a set of interconnected reactive subsystems. The subsystem verification task is to verify an implementation of the subsystem against t...
Kyle L. Nelson, Alok Jain, Randal E. Bryant
CAL
2002
13 years 8 months ago
Exploiting Fixed Programs in Embedded Systems: A Loop Cache Example
Embedded systems commonly execute one program for their lifetime. Designing embedded system architectures with configurable components, such that those components can be tuned to t...
Ann Gordon-Ross, Susan Cotterell, Frank Vahid