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CODES
2011
IEEE
12 years 7 months ago
Dynamic, multi-core cache coherence architecture for power-sensitive mobile processors
Today, mobile smartphones are expected to be able to run the same complex, memory-intensive applications that were originally designed and coded for general-purpose processors. Ho...
Garo Bournoutian, Alex Orailoglu
ASPLOS
1996
ACM
13 years 11 months ago
Exploiting Dual Data-Memory Banks in Digital Signal Processors
Over the past decade, digital signal processors (DSPs) have emerged as the processors of choice for implementing embedded applications in high-volume consumer products. Through th...
Mazen A. R. Saghir, Paul Chow, Corinna G. Lee
VLSID
2008
IEEE
138views VLSI» more  VLSID 2008»
14 years 7 months ago
Memory Architecture Exploration Framework for Cache Based Embedded SOC
Today's feature-rich multimedia products require embedded system solution with complex System-on-Chip (SoC) to meet market expectations of high performance at a low cost and l...
T. S. Rajesh Kumar, C. P. Ravikumar, R. Govindaraj...
COMPUTER
2000
138views more  COMPUTER 2000»
13 years 7 months ago
Making Pointer-Based Data Structures Cache Conscious
Processor and memory technology trends portend a continual increase in the relative cost of accessing main memory. Machine designers have tried to mitigate the effect of this tren...
Trishul M. Chilimbi, Mark D. Hill, James R. Larus
RTAS
1996
IEEE
13 years 11 months ago
Efficient worst case timing analysis of data caching
Recent progress in worst case timing analysis of programs has made it possible to perform accurate timing analysis of pipelined execution and instruction caching, which is necessa...
Sung-Kwan Kim, Sang Lyul Min, Rhan Ha