276 search results - page 22 / 56 » Memory Organization for Improved Data Cache Performance in E... |
DATE
2011
IEEE
13 years 7 days ago
2011
IEEE
Current processors are optimized for average case performance, often leading to a high worst-case execution time (WCET). Many architectural features that increase the average case...
PLDI
2005
ACM
14 years 2 months ago
2005
ACM
This paper describes Automatic Pool Allocation, a transformation framework that segregates distinct instances of heap-based data structures into seperate memory pools and allows h...
ISVLSI
2003
IEEE
14 years 1 months ago
2003
IEEE
Previous work has shown that cache line sizes impact performance differently for different desktop programs – some programs work better with small line sizes, others with larger...
MICRO
2009
IEEE
14 years 3 months ago
2009
IEEE
3D-integration is a promising technology to help combat the “Memory Wall” in future multi-core processors. Past work has considered using 3D-stacked DRAM as a large last-level...
IWMM
2011
Springer
12 years 11 months ago
2011
Springer
Multiprocessors based on processors with multiple cores usually include a non-uniform memory architecture (NUMA); even current 2-processor systems with 8 cores exhibit non-uniform...