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HPCA
2005
IEEE
14 years 8 months ago
Using Virtual Load/Store Queues (VLSQs) to Reduce the Negative Effects of Reordered Memory Instructions
The use of large instruction windows coupled with aggressive out-oforder and prefetching capabilities has provided significant improvements in processor performance. In this paper...
Aamer Jaleel, Bruce L. Jacob
BIOCOMP
2006
13 years 10 months ago
Performance of Sequence Alignment Bioinformatics Applications on General Purpose Processors: A Case Study
- Aligning specific sequences against other known sequences in a database is a central aspect of bioinformatics. New experimental data being added continuously to these databases n...
Pradeep Nair, Eugene John
VLDB
2004
ACM
126views Database» more  VLDB 2004»
14 years 1 months ago
STEPS towards Cache-resident Transaction Processing
Online transaction processing (OLTP) is a multibillion dollar industry with high-end database servers employing state-of-the-art processors to maximize performance. Unfortunately,...
Stavros Harizopoulos, Anastassia Ailamaki
IPPS
2000
IEEE
14 years 27 days ago
Using Switch Directories to Speed Up Cache-to-Cache Transfers in CC-NUMA Multiprocessors
In this paper, we propose a novel hardware caching technique, called switch directory, to reduce the communication latency in CC-NUMA multiprocessors. The main idea is to implemen...
Ravi R. Iyer, Laxmi N. Bhuyan, Ashwini K. Nanda
ISCA
2009
IEEE
146views Hardware» more  ISCA 2009»
14 years 3 months ago
Multi-execution: multicore caching for data-similar executions
While microprocessor designers turn to multicore architectures to sustain performance expectations, the dramatic increase in parallelism of such architectures will put substantial...
Susmit Biswas, Diana Franklin, Alan Savage, Ryan D...