276 search results - page 28 / 56 » Memory Organization for Improved Data Cache Performance in E... |
ACISICIS
2005
IEEE
14 years 2 months ago
2005
IEEE
Simultaneous Multithreaded (SMT) processors improve the instruction throughput by allowing fetching and running instructions from several threads simultaneously at a single cycle....
IPPS
1999
IEEE
14 years 23 days ago
1999
IEEE
Software distributed shared memory (DSM) systems have successfully provided the illusion of shared memory on distributed memory machines. However, most software DSM systems use th...
EMSOFT
2005
Springer
14 years 2 months ago
2005
Springer
Recent research in embedded computing indicates that packing multiple processor cores on the same die is an effective way of utilizing the ever-increasing number of transistors. T...
ISCA
1999
IEEE
14 years 23 days ago
1999
IEEE
By optimizing data layout at run-time, we can potentially enhance the performance of caches by actively creating spatial locality, facilitating prefetching, and avoiding cache con...
VALUETOOLS
2006
ACM
14 years 2 months ago
2006
ACM
Cache locality optimization is an efficient way for reducing the idle time of modern processors in waiting for needed data. This kind of optimization can be achieved either on the...