276 search results - page 50 / 56 » Memory Organization for Improved Data Cache Performance in E... |
JILP
2000
13 years 8 months ago
2000
Load latency remains a signi cant bottleneck in dynamically scheduled pipelined processors. Load speculation techniques have been proposed to reduce this latency. Dependence Predi...
VIIP
2001
13 years 9 months ago
2001
Graphics cards exercise increasingly more computing power and are highly optimized for high data transfer volumes. In contrast typical workstations perform badly when data exceeds...
HPDC
1999
IEEE
14 years 22 days ago
1999
IEEE
In this paper, we present the design and implementation of Dodo, an e cient user-level system for harvesting idle memory in o -the-shelf clusters of workstations. Dodo enables dat...
JSA
2000
13 years 8 months ago
2000
In this article, the problem of finding a tight estimate on the worst-case execution time (WCET) of a real-time program is addressed. The analysis is focused on straight-line code...
ICCAD
2008
IEEE
14 years 5 months ago
2008
IEEE
— As transistor sizes continue to shrink and the number of transistors per chip keeps increasing, chip multiprocessors (CMPs) are becoming a promising alternative to remain on th...