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FCCM
1997
IEEE
103views VLSI» more  FCCM 1997»
13 years 12 months ago
An FPGA architecture for DRAM-based systolic computations
We propose an FPGA chip architecture based on a conventional FPGA logic array core, in which I/O pins are clocked at a much higher rate than that of the logic array that they serv...
Norman Margolus
PPOPP
1997
ACM
13 years 12 months ago
LoPC: Modeling Contention in Parallel Algorithms
Parallel algorithm designers need computational models that take first order system costs into account, but are also simple enough to use in practice. This paper introduces the L...
Matthew Frank, Anant Agarwal, Mary K. Vernon
EURODAC
1994
IEEE
209views VHDL» more  EURODAC 1994»
13 years 11 months ago
MOS VLSI circuit simulation by hardware accelerator using semi-natural models
- The accelerator is destined to circuit-level simulation of digital and analog/digital MOS VLSI'c containing of up to 100 thousand transistors (with 16 Mb RAM host-machine). ...
Victor V. Denisenko
ANCS
2007
ACM
13 years 11 months ago
Curing regular expressions matching algorithms from insomnia, amnesia, and acalculia
The importance of network security has grown tremendously and a collection of devices have been introduced, which can improve the security of a network. Network intrusion detectio...
Sailesh Kumar, Balakrishnan Chandrasekaran, Jonath...
HOTOS
2007
IEEE
13 years 11 months ago
HotComments: How to Make Program Comments More Useful?
Program comments have long been used as a common practice for improving inter-programmer communication and code readability, by explicitly specifying programmers' intentions ...
Lin Tan, Ding Yuan, Yuanyuan Zhou