42 search results - page 4 / 9 » Memory Requirement Optimization with Loop Fusion and Loop Sh... |
PLDI
2004
ACM
14 years 27 days ago
2004
ACM
When vectorizing for SIMD architectures that are commonly employed by today’s multimedia extensions, one of the new challenges that arise is the handling of memory alignment. Pr...
ICCAD
2001
IEEE
14 years 4 months ago
2001
IEEE
In this paper we describe a software pipelining framework, CALiBeR (Cluster Aware Load Balancing Retiming Algorithm), suitable for compilers targeting clustered embedded VLIW proc...
ASPLOS
2008
ACM
13 years 9 months ago
2008
ACM
The recent shift in the industry towards chip multiprocessor (CMP) designs has brought the need for multi-threaded applications to mainstream computing. As observed in several lim...
CODES
2000
IEEE
13 years 12 months ago
2000
IEEE
Memory interleaving is a cost-efficient approach to increase bandwidth. Improving data access locality and reducing memory access conflicts are two important aspects to achieve hi...
CASES
2006
ACM
14 years 1 months ago
2006
ACM
In this paper, we propose a fully automatic dynamic scratchpad memory (SPM) management technique for instructions. Our technique loads required code segments into the SPM on deman...