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» Memory access optimizations in instruction-set simulators
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PDPTA
2000
13 years 8 months ago
Evaluation of Neural and Genetic Algorithms for Synthesizing Parallel Storage Schemes
Exploiting compile time knowledge to improve memory bandwidth can produce noticeable improvements at run-time [13, 1]. Allocating the data structure [13] to separate memories when...
Mayez A. Al-Mouhamed, Husam Abu-Haimed
ISPASS
2008
IEEE
14 years 1 months ago
Pinpointing and Exploiting Opportunities for Enhancing Data Reuse
—The potential for improving the performance of data-intensive scientific programs by enhancing data reuse in cache is substantial because CPUs are significantly faster than me...
Gabriel Marin, John M. Mellor-Crummey
NCA
2009
IEEE
14 years 1 months ago
A Distributed Algorithm for Web Content Replication
—Web caching and replication techniques increase accessibility of Web contents and reduce Internet bandwidth requirements. In this paper, we are considering the replica placement...
Sharrukh Zaman, Daniel Grosu
CPHYSICS
2006
124views more  CPHYSICS 2006»
13 years 6 months ago
Collision-free spatial hash functions for structural analysis of billion-vertex chemical bond networks
State-of-the-art molecular dynamics (MD) simulations generate massive datasets involving billion-vertex chemical bond networks, which makes data mining based on graph algorithms s...
Cheng Zhang, Bhupesh Bansal, Paulo S. Branicio, Ra...
HIPEAC
2011
Springer
12 years 6 months ago
NoC-aware cache design for multithreaded execution on tiled chip multiprocessors
In chip multiprocessors (CMPs), data accesslatency dependson the memory hierarchy organization, the on-chip interconnect (NoC), and the running workload. Reducing data access late...
Ahmed Abousamra, Alex K. Jones, Rami G. Melhem