86 search results - page 7 / 18 » Memory access optimizations in instruction-set simulators |
CAL
2007
13 years 6 months ago
2007
Current on-chip block-centric memory hierarchies exploit access patterns at the fine-grain scale of small blocks. Several recently proposed memory hierarchy enhancements for coher...
IPPS
2008
IEEE
14 years 1 months ago
2008
IEEE
We present an auto-tuning approach to optimize application performance on emerging multicore architectures. The methodology extends the idea of searchbased performance optimizatio...
IPPS
1999
IEEE
13 years 11 months ago
1999
IEEE
Block-wise access to data is a central theme in the design of efficient external memory (EM) algorithms. A second important issue, when more than one disk is present, is fully par...
COMPUTER
2002
13 years 6 months ago
2002
tail defines the level of abstraction used to implement the model's components. A highly detailed model will faithfully simulate all aspects of machine operation, whether or n...
JUCS
2000
13 years 6 months ago
2000
: This paper presents an evaluation of our Scheduled Dataflow (SDF) Processor. Recent focus in the field of new processor architectures is mainly on VLIW (e.g. IA-64), superscalar ...