86 search results - page 9 / 18 » Memory access optimizations in instruction-set simulators |
HPCA
2002
IEEE
13 years 11 months ago
2002
IEEE
Configurations of contemporary DRAM memory systems become increasingly complex. A recent study [5] shows that application performance is highly sensitive to choices of configura...
ISCA
1999
IEEE
13 years 11 months ago
1999
IEEE
Providing adequate data bandwidth is extremely important for a wide-issue superscalar processor to achieve its full performance potential. Adding a large number of ports to a data...
CGO
2007
IEEE
14 years 1 months ago
2007
IEEE
Modern memory systems play a critical role in the performance of applications, but a detailed understanding of the application behavior in the memory system is not trivial to atta...
IWOMP
2007
Springer
14 years 26 days ago
2007
Springer
The Cell processor is a heterogeneous multi-core processor with one Power Processing Engine (PPE) core and eight Synergistic Processing Engine (SPE) cores. Each SPE has a directly...
EUROPAR
2004
Springer
14 years 3 days ago
2004
Springer
This paper describes a monitoring environment that enables the analysis of memory access behavior of applications in a selective way with a potentially very high degree of detail. ...