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ISPASS
2010
IEEE
14 years 1 days ago
StatStack: Efficient modeling of LRU caches
The identification of the memory gap in terms of the relatively slow memory accesses put a focus on cache
David Eklov, Erik Hagersten
IFIP
2010
Springer
13 years 2 months ago
Model Checking of Concurrent Algorithms: From Java to C
Concurrent software is difficult to verify. Because the thread schedule is not controlled by the application, testing may miss defects that occur under specific thread schedules. T...
Cyrille Artho, Masami Hagiya, Watcharin Leungwatta...
HPCA
2002
IEEE
14 years 8 months ago
A New Memory Monitoring Scheme for Memory-Aware Scheduling and Partitioning
We propose a low overhead, on-line memory monitoring scheme utilizing a set of novel hardware counters. The counters act like pressure gauges indicating the marginal gain in the n...
G. Edward Suh, Srinivas Devadas, Larry Rudolph
ISCA
1992
IEEE
88views Hardware» more  ISCA 1992»
13 years 11 months ago
Hiding Memory Latency using Dynamic Scheduling in Shared-Memory Multiprocessors
Kourosh Gharachorloo, Anoop Gupta, John L. Henness...