3202 search results - page 468 / 641 » Memory access scheduling |
HPCA
1997
IEEE
14 years 11 days ago
1997
IEEE
Processors with write-through caches typically require a write buffer to hide the write latency to the next level of memory hierarchy and to reduce write traffic. A write buffer ...
ICPP
1993
IEEE
14 years 8 days ago
1993
IEEE
: This paper presents a Data-Distributed Execution approach that exploits interation-level parallelism in loops operating over arrays. It performs data-dependency analysis, based o...
DATE
2004
IEEE
13 years 12 months ago
2004
IEEE
In this paper, we explore the requirements of emerging complex SoC's and describe StepNP, an experimental flexible, multi-processor SoC platform targeted towards communicatio...
EUC
2006
Springer
13 years 11 months ago
2006
Springer
As the ever-increasing gap between the speed of processor and the speed of memory has become the cause of one of primary bottlenecks of computer systems, modern architecture system...
ICS
2000
Tsinghua U.
13 years 11 months ago
2000
Tsinghua U.
Loop fusion is important to optimizing compilers because it is an important tool in managing the memory hierarchy. By fusing loops that use the same data elements, we can reduce t...