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FCCM
2009
IEEE
171views VLSI» more  FCCM 2009»
14 years 2 months ago
Accelerating SPICE Model-Evaluation using FPGAs
—Single-FPGA spatial implementations can provide an order of magnitude speedup over sequential microprocessor implementations for data-parallel, floating-point computation in SP...
Nachiket Kapre, André DeHon
MEMOCODE
2008
IEEE
14 years 2 months ago
Static Deadlock Detection for the SHIM Concurrent Language
Concurrent programming languages are becoming mandatory with the advent of multi-core processors. Two major concerns in any concurrent program are data races and deadlocks. Each a...
Nalini Vasudevan, Stephen A. Edwards
CGO
2007
IEEE
14 years 2 months ago
Iterative Optimization in the Polyhedral Model: Part I, One-Dimensional Time
Emerging microprocessors offer unprecedented parallel computing capabilities and deeper memory hierarchies, increasing the importance of loop transformations in optimizing compile...
Louis-Noël Pouchet, Cédric Bastoul, Al...
CODES
2007
IEEE
14 years 2 months ago
Complex task activation schemes in system level performance analysis
The design and analysis of today’s complex real-time systems requires advanced methods. Due to ever growing functionality, hardware complexity and component interaction, applyin...
Wolfgang Haid, Lothar Thiele
IPPS
2007
IEEE
14 years 2 months ago
Domain Decomposition vs. Master-Slave in Apparently Homogeneous Systems
This paper investigates the utilization of the master-slave (MS) paradigm as an alternative to domain decomposition (DD) methods for parallelizing lattice gauge theory (LGT) model...
Cyril Banino-Rokkones