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IPPS
2007
IEEE
14 years 2 months ago
A Power-Aware Prediction-Based Cache Coherence Protocol for Chip Multiprocessors
Snoopy cache coherence protocols broadcast requests to all nodes, reducing the latency of cache to cache transfer misses at the expense of increasing interconnect power. We propos...
Ehsan Atoofian, Amirali Baniasadi
MSS
2007
IEEE
83views Hardware» more  MSS 2007»
14 years 2 months ago
The RAM Enhanced Disk Cache Project (REDCAP)
This paper presents the RAM Enhanced Disk Cache Project, REDCAP, a new cache of disk blocks which reduces the read I/O time by using a small portion of the main memory. The essent...
Pilar Gonzalez-Ferez, Juan Piernas, Toni Cortes
VTS
2007
IEEE
103views Hardware» more  VTS 2007»
14 years 2 months ago
At-Speed Testing of Core-Based System-on-Chip Using an Embedded Micro-Tester
In SoC designs, limited test access to internal cores, lowcost external tester’s lack of accuracy and slow frequencies make application of at-speed tests impractical. Therefore,...
Matthieu Tuna, Mounir Benabdenbi, Alain Greiner
DAMON
2007
Springer
14 years 2 months ago
In-memory grid files on graphics processors
Recently, graphics processing units, or GPUs, have become a viable alternative as commodity, parallel hardware for generalpurpose computing, due to their massive data-parallelism,...
Ke Yang, Bingsheng He, Rui Fang, Mian Lu, Naga K. ...
DRM
2007
Springer
14 years 2 months ago
Data structures for limited oblivious execution of programs while preserving locality of reference
We introduce a data structure for program execution under a limited oblivious execution model. For fully oblivious execution along the lines of Goldreich and Ostrovsky [2], one tr...
Avinash V. Varadarajan, Ramarathnam Venkatesan, C....