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VLDB
2001
ACM
121views Database» more  VLDB 2001»
14 years 9 days ago
Weaving Relations for Cache Performance
Relational database systems have traditionally optimzed for I/O performance and organized records sequentially on disk pages using the N-ary Storage Model (NSM) (a.k.a., slotted p...
Anastassia Ailamaki, David J. DeWitt, Mark D. Hill...
HPCA
2000
IEEE
14 years 9 days ago
Modified LRU Policies for Improving Second-Level Cache Behavior
Main memory accesses continue to be a significant bottleneck for applications whose working sets do not fit in second-level caches. With the trend of greater associativity in seco...
Wayne A. Wong, Jean-Loup Baer
IPPS
2000
IEEE
14 years 8 days ago
Using Switch Directories to Speed Up Cache-to-Cache Transfers in CC-NUMA Multiprocessors
In this paper, we propose a novel hardware caching technique, called switch directory, to reduce the communication latency in CC-NUMA multiprocessors. The main idea is to implemen...
Ravi R. Iyer, Laxmi N. Bhuyan, Ashwini K. Nanda
IPPS
2000
IEEE
14 years 8 days ago
Monotonic Counters: A New Mechanism for Thread Synchronization
Only a handful of fundamental mechanisms for synchronizing the access of concurrent threads to shared memory are widely implemented and used. These include locks, condition variab...
John Thornley, K. Mani Chandy
MICRO
2000
IEEE
80views Hardware» more  MICRO 2000»
14 years 8 days ago
Silent stores for free
Silent store instructions write values that exactly match the values that are already stored at the memory address that is being written. A recent study reveals that significant ...
Kevin M. Lepak, Mikko H. Lipasti