Sciweavers

3202 search results - page 586 / 641
» Memory access scheduling
Sort
View
ISLPED
2004
ACM
151views Hardware» more  ISLPED 2004»
14 years 1 months ago
Dynamic voltage and frequency scaling based on workload decomposition
This paper presents a technique called “workload decomposition” in which the CPU workload is decomposed in two parts: on-chip and off-chip. The on-chip workload signifies the ...
Kihwan Choi, Ramakrishna Soma, Massoud Pedram
LCTRTS
2004
Springer
14 years 1 months ago
Spinach: a liberty-based simulator for programmable network interface architectures
This paper presents Spinach, a new simulator toolset specifically designed to target programmable network interface architectures. Spinach models both system components that are ...
Paul Willmann, Michael Brogioli, Vijay S. Pai
ICS
2003
Tsinghua U.
14 years 1 months ago
Inferential queueing and speculative push for reducing critical communication latencies
Communication latencies within critical sections constitute a major bottleneck in some classes of emerging parallel workloads. In this paper, we argue for the use of Inferentially...
Ravi Rajwar, Alain Kägi, James R. Goodman
EUROSYS
2010
ACM
14 years 27 days ago
Residue objects: a challenge to web browser security
A complex software system typically has a large number of objects in the memory, holding references to each other to implement an object model. Deciding when the objects should be...
Shuo Chen, Hong Chen, Manuel Caballero
INFOCOM
2002
IEEE
14 years 22 days ago
Scalable IP Lookup for Programmable Routers
Abstract— Continuing growth in optical link speeds places increasing demands on the performance of Internet routers, while deployment of embedded and distributed network services...
David E. Taylor, John W. Lockwood, Todd S. Sproull...