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DSD
2004
IEEE
129views Hardware» more  DSD 2004»
15 years 8 months ago
Functional Validation of Programmable Architectures
Validation of programmable architectures, consisting of processor cores, coprocessors, and memory subsystems, is one of the major bottlenecks in current Systemon-Chip design metho...
Prabhat Mishra, Nikil D. Dutt
ALGORITHMICA
2007
145views more  ALGORITHMICA 2007»
15 years 4 months ago
Counting Integer Points in Parametric Polytopes Using Barvinok's Rational Functions
Abstract Many compiler optimization techniques depend on the ability to calculate the number of elements that satisfy certain conditions. If these conditions can be represented by ...
Sven Verdoolaege, Rachid Seghir, Kristof Beyls, Vi...
BMCBI
2010
109views more  BMCBI 2010»
15 years 4 months ago
FPGA acceleration of the phylogenetic likelihood function for Bayesian MCMC inference methods
Background: Likelihood (ML)-based phylogenetic inference has become a popular method for estimating the evolutionary relationships among species based on genomic sequence data. Th...
Stephanie Zierke, Jason D. Bakos
SIAMMAX
2011
157views more  SIAMMAX 2011»
14 years 7 months ago
Deflated Restarting for Matrix Functions
We investigate an acceleration technique for restarted Krylov subspace methods for computing the action of a function of a large sparse matrix on a vector. Its effect is to ultima...
Michael Eiermann, Oliver G. Ernst, Stefan Güt...
ICIP
2004
IEEE
16 years 5 months ago
Distributed compression of the plenoptic function
In this paper, we consider the problem of distributed compression in camera sensor networks. Due to the spatial proximity of the different cameras, acquired images can be highly d...
Nicolas Gehrig, Pier Luigi Dragotti