109 search results - page 6 / 22 » Microcode Generation for Flexible Parallel Target Architectu... |
IMR
1999
Springer
13 years 11 months ago
1999
Springer
The primary focus of this project is to design and implement a parallel framework for an unstructured mesh generator based on the advancing front method (AFM). In particular, we t...
IPPS
2007
IEEE
14 years 1 months ago
2007
IEEE
This paper explores generating efficient, portable HighSpeed Producer Consumer (HSPC) code on current shared memory architectures: Chip Multi-Processors (CMP), Simultaneous Multi...
IPPS
1998
IEEE
13 years 11 months ago
1998
IEEE
We describe a family of reconfigurable parallel architectures for logic emulation. They are supposed to be applicable like conventional FPGAs, while covering a larger range of circ...
INFOCOM
2007
IEEE
14 years 1 months ago
2007
IEEE
Next-generation high-end Network Processors (NP) must address demands from both diversified applications and ever-increasing traffic pressure. One major challenge is to design an e...
LCPC
1999
Springer
13 years 11 months ago
1999
Springer
The traditional target machine of a parallelizing compiler can execute code sections either serially or in parallel. In contrast, targeting the generated code to a speculative para...