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ASPDAC
2007
ACM
135views Hardware» more  ASPDAC 2007»
13 years 10 months ago
A Parameterized Architecture Model in High Level Synthesis for Image Processing Applications
- Most image processing applications are computationally intensive and data intensive. Reconfigurable hardware boards provide a convenient and flexible solution to speed up these a...
Yazhuo Dong, Yong Dou
CCGRID
2004
IEEE
13 years 10 months ago
The virtual resource manager: an architecture for SLA-aware resource management
The next generation Grid will demand the Grid middleware to provide flexibility, transparency, and reliability. This implies the appliance of service level agreements to guarantee...
Lars-Olof Burchard, Matthias Hovestadt, Odej Kao, ...
FPL
2008
Springer
116views Hardware» more  FPL 2008»
13 years 8 months ago
NOC architecture design for multi-cluster chips
For the next generation of multi-core processors, the onchip interconnection networks must be efficient to achieve high data throughput and performance. Moreover, these interconne...
Henrique C. Freitas, Philippe Olivier Alexandre Na...
IEEECIT
2010
IEEE
13 years 5 months ago
SAT: A Stream Architecture Template for Embedded Applications
- The increase of embedded applications complexity has demanded hardware more flexible while providing higher performance. Reconfigurable architectures and stream processing have b...
Qianming Yang, Nan Wu, Mei Wen, Yi He, Huayou Su, ...
IPPS
2002
IEEE
13 years 11 months ago
A Performance Optimization Framework for Compilation of Tensor Contraction Expressions into Parallel Programs
This paper discusses a program synthesis system to facilitate the generation of high-performance parallel programs for a class of computations encountered in quantum chemistry and...
Gerald Baumgartner, David E. Bernholdt, Daniel Coc...