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ICCD
2005
IEEE
134views Hardware» more  ICCD 2005»
14 years 4 months ago
Architectural Considerations for Energy Efficiency
The formal analysis of parallelism and pipelining is performed on an 8-bit Add-Compare-Select element of a Viterbi decoder. The results are quantified through a study of the delay...
Hoang Q. Dao, Bart R. Zeydel, Vojin G. Oklobdzija
DATE
2011
IEEE
223views Hardware» more  DATE 2011»
12 years 11 months ago
Towards a Time-predictable Dual-Issue Microprocessor: The Patmos Approach
Current processors are optimized for average case performance, often leading to a high worst-case execution time (WCET). Many architectural features that increase the average case...
Martin Schoeberl, Pascal Schleuniger, Wolfgang Puf...
AINA
2007
IEEE
14 years 2 months ago
Sim-PowerCMP: A Detailed Simulator for Energy Consumption Analysis in Future Embedded CMP Architectures
Continuous improvements in integration scale have made major microprocessor vendors to move to designs that integrate several processor cores on the same chip. Chip-multiprocessor...
Antonio Flores, Juan L. Aragón, Manuel E. A...
VEE
2006
ACM
178views Virtualization» more  VEE 2006»
14 years 1 months ago
Impact of virtual execution environments on processor energy consumption and hardware adaptation
During recent years, microprocessor energy consumption has been surging and efforts to reduce power and energy have received a lot of attention. At the same time, virtual executio...
Shiwen Hu, Lizy Kurian John
ASYNC
2004
IEEE
102views Hardware» more  ASYNC 2004»
13 years 11 months ago
Non-Uniform Access Asynchronous Register Files
Register files of microprocessors have often been cited as performance bottlenecks and significant consumers of energy. The robust and modular nature of quasi-delay insensitive (Q...
David Fang, Rajit Manohar