Sciweavers

1165 search results - page 212 / 233
» Middleware in Modern High Performance Computing System Archi...
Sort
View
IPPS
2000
IEEE
14 years 1 months ago
Fault-Tolerant Distributed-Shared-Memory on a Broadcast-Based Interconnection Network
The Simultaneous Optical Multiprocessor Exchange Bus (SOME-Bus) is a low-latency, high-bandwidth interconnection network which directly links arbitrary pairs of processor nodes wit...
Diana Hecht, Constantine Katsinis
CF
2007
ACM
14 years 24 days ago
Accelerating memory decryption and authentication with frequent value prediction
This paper presents a novel architectural technique to hide fetch latency overhead of hardware encrypted and authenticated memory. A number of recent secure processor designs have...
Weidong Shi, Hsien-Hsin S. Lee
ACSAC
2000
IEEE
14 years 1 months ago
Enabling Secure On-Line DNS Dynamic Update
Domain Name System (DNS) is the system for the mapping between easily memorizable host names and their IP addresses. Due to its criticality, security extensions to DNS have been p...
Xunhua Wang, Yih Huang, Yvo Desmedt, David Rine
MOBICOM
2006
ACM
14 years 2 months ago
IQU: practical queue-based user association management for WLANs
Flash crowds and high concentrations of users in wireless LANs (WLANs) cause significant interference problems and unsustainable load at access points. This leads to poor connect...
Amit P. Jardosh, Kimaya Mittal, Krishna N. Ramacha...
HPCA
2007
IEEE
14 years 9 months ago
A Scalable, Non-blocking Approach to Transactional Memory
Transactional Memory (TM) provides mechanisms that promise to simplify parallel programming by eliminating the need for locks and their associated problems (deadlock, livelock, pr...
Hassan Chafi, Jared Casper, Brian D. Carlstrom, Au...