588 search results - page 115 / 118 » Minimality Results for the Spatial Logics |
ICCAD
2003
IEEE
14 years 4 months ago
2003
IEEE
Routing for FPGAs has been a very challenging problem due to the limitation of routing resources. Although the FPGA routing problem has been researched extensively, most algorithm...
FPGA
2010
ACM
14 years 4 months ago
2010
ACM
Guarded evaluation is a power reduction technique that involves identifying sub-circuits (within a larger circuit) whose inputs can be held constant (guarded) at specific times d...
DAC
2009
ACM
14 years 2 months ago
2009
ACM
Manufacturing process variability impacts the performance of synchronous logic circuits by means of its effect on both clock network and functional block delays. Typically, varia...
IWNAS
2008
IEEE
14 years 1 months ago
2008
IEEE
— Distributed Hash Table (DHT) based algorithms have been proposed to solve the routing issues in large-scale Peer-to-Peer (P2P) applications. DHT systems create an elegant Peer-...
BROADNETS
2007
IEEE
14 years 1 months ago
2007
IEEE
— Network dimensioning for wavelength-routed WDM networks has been extensively studied to maximize connection acceptance rate while minimizing the total cost. However, Internet s...