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» Missing the Memory Wall: The Case for Processor Memory Integ...
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ECRTS
2006
IEEE
14 years 1 months ago
WCET-Centric Software-controlled Instruction Caches for Hard Real-Time Systems
Cache memories have been extensively used to bridge the gap between high speed processors and relatively slower main memories. However, they are sources of predictability problems...
Isabelle Puaut
DEBS
2010
ACM
13 years 11 months ago
Evaluation of streaming aggregation on parallel hardware architectures
We present a case study parallelizing streaming aggregation on three different parallel hardware architectures. Aggregation is a performance-critical operation for data summarizat...
Scott Schneider, Henrique Andrade, Bugra Gedik, Ku...
ISCA
2005
IEEE
90views Hardware» more  ISCA 2005»
14 years 1 months ago
Optimizing Replication, Communication, and Capacity Allocation in CMPs
Chip multiprocessors (CMPs) substantially increase capacity pressure on the on-chip memory hierarchy while requiring fast access. Neither private nor shared caches can provide bot...
Zeshan Chishti, Michael D. Powell, T. N. Vijaykuma...
CASES
2008
ACM
13 years 9 months ago
Reducing pressure in bounded DBT code caches
Dynamic binary translators (DBT) have recently attracted much attention for embedded systems. The effective implementation of DBT in these systems is challenging due to tight cons...
José Baiocchi, Bruce R. Childers, Jack W. D...
NDSS
2006
IEEE
14 years 1 months ago
Toward a Practical Data Privacy Scheme for a Distributed Implementation of the Smith-Waterman Genome Sequence Comparison Algorit
Volunteer distributed computations utilize spare processor cycles of personal computers that are connected to the Internet. The resulting platforms provide computational power pre...
Doug Szajda, Michael Pohl, Jason Owen, Barry G. La...