1222 search results - page 197 / 245 » Mistreatment-resilient distributed caching |
FCSC
2007
13 years 9 months ago
2007
Data access latency is an important metric of system performance in data grid. By means of efficient replication strategy, the amount of data transferred in wide area network will ...
CCGRID
2010
IEEE
13 years 8 months ago
2010
IEEE
—While computing speed continues increasing rapidly, data-access technology is lagging behind. Data-access delay, not the processor speed, becomes the leading performance bottlen...
IPPS
2010
IEEE
13 years 7 months ago
2010
IEEE
It is possible to implement the parallel random access machine (PRAM) on a chip multiprocessor (CMP) efficiently with an emulated shared memory (ESM) architecture to gain easy par...
IPPS
2010
IEEE
13 years 7 months ago
2010
IEEE
Line-rate data traffic monitoring in high-speed networks is essential for network management. To satisfy the line-rate requirement, one can leverage multi-core architectures to par...
IEEEPACT
2009
IEEE
13 years 6 months ago
2009
IEEE
Abstract--Chip-MultiProcessor (CMP) architectures are becoming more and more popular as an alternative to the traditional processors that only extract instruction-level parallelism...