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WDAG
2005
Springer
82views Algorithms» more  WDAG 2005»
14 years 1 months ago
Distributed Transactional Memory for Metric-Space Networks
Transactional Memory is a concurrent programming API in which concurrent threads synchronize via transactions (instead of locks). Although this model has mostly been studied in the...
Maurice Herlihy, Ye Sun
MICRO
2006
IEEE
145views Hardware» more  MICRO 2006»
14 years 2 months ago
Virtually Pipelined Network Memory
We introduce virtually-pipelined memory, an architectural technique that efficiently supports high-bandwidth, uniform latency memory accesses, and high-confidence throughput eve...
Banit Agrawal, Timothy Sherwood
DSN
2007
IEEE
14 years 11 days ago
A Real-Time Network Traffic Profiling System
This paper presents the design and implementation of a real-time behavior profiling system for high-speed Internet links. The profiling system uses flow-level information from con...
Kuai Xu, Feng Wang 0002, Supratik Bhattacharyya, Z...
CASES
2006
ACM
14 years 5 days ago
High-performance packet classification algorithm for many-core and multithreaded network processor
Packet classification is crucial for the Internet to provide more value-added services and guaranteed quality of service. Besides hardware-based solutions, many software-based cla...
Duo Liu, Bei Hua, Xianghui Hu, Xinan Tang
TVLSI
2008
133views more  TVLSI 2008»
13 years 8 months ago
A Medium-Grain Reconfigurable Architecture for DSP: VLSI Design, Benchmark Mapping, and Performance
Reconfigurable hardware has become a well-accepted option for implementing digital signal processing (DSP). Traditional devices such as field-programmable gate arrays offer good fi...
Mitchell J. Myjak, José G. Delgado-Frias