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ISCA
2008
IEEE
170views Hardware» more  ISCA 2008»
14 years 2 months ago
Polymorphic On-Chip Networks
As the number of cores per die increases, be they processors, memory blocks, or custom accelerators, the on-chip interconnect the cores use to communicate gains importance. We beg...
Martha Mercaldi Kim, John D. Davis, Mark Oskin, To...
ICS
2009
Tsinghua U.
14 years 3 months ago
Designing multi-socket systems using silicon photonics
Future single-board multi-socket systems may be unable to deliver the needed memory bandwidth electrically due to power limitations, which will hurt their ability to drive perform...
Scott Beamer, Krste Asanovic, Christopher Batten, ...
FPGA
2009
ACM
168views FPGA» more  FPGA 2009»
13 years 6 months ago
Large-scale wire-speed packet classification on FPGAs
Multi-field packet classification is a key enabling function of a variety of network applications, such as firewall processing, Quality of Service differentiation, traffic billing...
Weirong Jiang, Viktor K. Prasanna
CF
2007
ACM
14 years 13 days ago
Massively parallel processing on a chip
MppSoC is a SIMD architecture composed of a grid of processors and memories connected by a X-Net neighbourhood network and a general purpose global router. MppSoC is an evolution ...
Philippe Marquet, Simon Duquennoy, Sébastie...
FPL
2006
Springer
120views Hardware» more  FPL 2006»
14 years 3 days ago
Regular Expression Software Deceleration for Intrusion Detection Systems
The use of reconfigurable hardware for network security applications has recently made great strides as FPGA devices have provided larger and faster resources. Regular expressions...
Zachary K. Baker, Viktor K. Prasanna, Hong-Jip Jun...