262 search results - page 19 / 53 » Mnemosyne: Designing and Implementing Network Short-Term Mem... |
HPCA
2011
IEEE
13 years 5 days ago
2011
IEEE
Traditional architectural designs are normally focused on CPUs and have been often decoupled from I/O considerations. They are inefficient for high-speed network processing with a...
HPDC
1997
IEEE
14 years 20 days ago
1997
IEEE
New network technology continues to improve both the latency and bandwidth of communication in computer clusters. The fastest high-speed networks approach or exceed the I/O bus ba...
ISCA
1998
IEEE
14 years 21 days ago
1998
IEEE
Alewife is a multiprocessor architecture that supports up to 512 processing nodes connected over a scalable and cost-effective mesh network at a constant cost per node. The MIT Al...
SNPD
2003
13 years 9 months ago
2003
This paper focuses on non-strict processing, optimization, and partial evaluation of MPI programs which use incremental data structures (ISs). We describe the design and implement...
TACAS
1998
Springer
14 years 20 days ago
1998
Springer
In this paper, we report on an application of the validation and veri cation tool kit Uppaal in the design and analysis of a prototype gear controller, carried out in a joint proje...