381 search results - page 15 / 77 » Model Checking Is Static Analysis of Modal Logic |
TASE
2007
IEEE
14 years 1 months ago
2007
IEEE
Software has been under scrutiny by the verification community from various angles in the recent past. There are two major algorithmic approaches to ensure the correctness of and...
TIME
2009
IEEE
14 years 2 months ago
2009
IEEE
The model checking problem for CTL is known to be P-complete (Clarke, Emerson, and Sistla (1986), see Schnoebelen (2002)). We consider fragments of CTL obtained by restricting the...
ICECCS
2007
IEEE
14 years 1 months ago
2007
IEEE
Identifying and resolving design problems in the early design phase can help ensure software quality and save costs. There are currently few tools for analyzing designs expressed ...
ICCAD
2007
IEEE
14 years 4 months ago
2007
IEEE
While the increasing need for addressing process variability in sub-90nm VLSI technologies has sparkled a large body of statistical timing and optimization research, the realizati...
ASPDAC
2006
ACM
14 years 1 months ago
2006
ACM
- One of the critical issues in MTCMOS design is how to estimate a circuit delay quickly. In this paper, we propose a delay modeling and static timing analysis (STA) methodology ta...