Abstract. The paper presents a partial order reduction method applicable to networks of timed automata. The advantage of the method is that it reduces both the number of explored c...
Bounded Model Checking (BMC) relies on solving a sequence of highly correlated Boolean satisfiability (SAT) problems, each of which corresponds to the existence of counter-example...
Chao Wang, HoonSang Jin, Gary D. Hachtel, Fabio So...
This paper examines the effect of technology scaling and microarchitectural trends on the rate of soft errors in CMOS memory and logic circuits. We describe and validate an end-to...
Premkishore Shivakumar, Michael Kistler, Stephen W...
The verification of quantitative aspects like performance and dependability by means of model checking has become an important and vivid area of research over the past decade. An ...
Stefan Blom, Boudewijn R. Haverkort, Matthias Kunt...
In summary, RDL is an intuitionistic temporal logic for the specification of requirements and design of time-dependent systems. Coverage of RDL includes a backward chaining theore...