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CONCUR
1999
Springer
14 years 3 months ago
Partial Order Reduction for Model Checking of Timed Automata
Abstract. The paper presents a partial order reduction method applicable to networks of timed automata. The advantage of the method is that it reduces both the number of explored c...
Marius Minea
DAC
2004
ACM
14 years 12 months ago
Refining the SAT decision ordering for bounded model checking
Bounded Model Checking (BMC) relies on solving a sequence of highly correlated Boolean satisfiability (SAT) problems, each of which corresponds to the existence of counter-example...
Chao Wang, HoonSang Jin, Gary D. Hachtel, Fabio So...
DSN
2002
IEEE
14 years 3 months ago
Modeling the Effect of Technology Trends on the Soft Error Rate of Combinational Logic
This paper examines the effect of technology scaling and microarchitectural trends on the rate of soft errors in CMOS memory and logic circuits. We describe and validate an end-to...
Premkishore Shivakumar, Michael Kistler, Stephen W...
ENTCS
2008
103views more  ENTCS 2008»
13 years 11 months ago
Distributed Markovian Bisimulation Reduction aimed at CSL Model Checking
The verification of quantitative aspects like performance and dependability by means of model checking has become an important and vivid area of research over the past decade. An ...
Stefan Blom, Boudewijn R. Haverkort, Matthias Kunt...
CONCUR
1989
Springer
14 years 3 months ago
Using the Temporal Logic RDL for Design Specifications
In summary, RDL is an intuitionistic temporal logic for the specification of requirements and design of time-dependent systems. Coverage of RDL includes a backward chaining theore...
Dov M. Gabbay, Ian M. Hodkinson, Anthony Hunter