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AAAI
2007
14 years 1 months ago
Logic for Automated Mechanism Design - A Progress Report
Over the past half decade, we have been exploring the use of logic in the specification and analysis of computational economic mechanisms. We believe that this approach has the p...
Michael Wooldridge, Thomas Ågotnes, Paul E. ...
CONCUR
2007
Springer
14 years 5 months ago
Pushdown Module Checking with Imperfect Information
The model checking problem for finite-state open systems (module checking) has been extensively studied in the literature, both in the context of environments with perfect and imp...
Benjamin Aminof, Aniello Murano, Moshe Y. Vardi
STACS
2007
Springer
14 years 5 months ago
Bounded-Variable Fragments of Hybrid Logics
Hybrid logics extend modal logics by first-order concepts, in particular they allow a limited use of variables. Unfortunately, in general, satisfiability for hybrid formulas is u...
Thomas Schwentick, Volker Weber
ENTCS
2007
108views more  ENTCS 2007»
13 years 11 months ago
Generating Java Compiler Optimizers Using Bidirectional CTL
There have been several research works that analyze and optimize programs using temporal logic. However, no evaluation of optimization time or execution time of these implementati...
Ling Fang, Masataka Sassa
DAC
2003
ACM
14 years 12 months ago
Behavioral consistency of C and verilog programs using bounded model checking
We present an algorithm that checks behavioral consistency between an ANSI-C program and a circuit given in Verilog using Bounded Model Checking. Both the circuit and the program ...
Edmund M. Clarke, Daniel Kroening, Karen Yorav