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» Model Checking Timed Automata with One or Two Clocks
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ICPADS
2005
IEEE
14 years 1 months ago
An Evaluation Mechanism for QoS Management in Wireless Systems
The evaluation of QoS requirements is one of the critical functions that span both the design and the run-time phases of QoS management. This paper presents an architecture for Qo...
Behzad Bordbar, Rachid Anane, Kozo Okano
TCS
2010
13 years 6 months ago
Canonical finite state machines for distributed systems
There has been much interest in testing from finite state machines (FSMs) as a result of their suitability for modelling or specifying state-based systems. Where there are multip...
Robert M. Hierons
VMCAI
2005
Springer
14 years 1 months ago
On the Complexity of Error Explanation
When a system fails to satisfy its specification, the model checker produces an error trace (or counter-example) that demonstrates an undesirable behavior, which is then used in d...
Nirman Kumar, Viraj Kumar, Mahesh Viswanathan
ICCAD
2001
IEEE
127views Hardware» more  ICCAD 2001»
14 years 4 months ago
What is the Limit of Energy Saving by Dynamic Voltage Scaling?
Dynamic voltage scaling (DVS) is a technique that varies the supply voltage and clock frequency based on the computation load to provide desired performance with the minimal amoun...
Gang Qu
IJNSEC
2010
133views more  IJNSEC 2010»
13 years 2 months ago
Verifiable Attribute Based Encryption
In this paper, we construct two verifiable attribute-based encryption (VABE) schemes. One is with a single authority, and the other is with multi authorities. Not only our schemes ...
Qiang Tang, Dongyao Ji