135 search results - page 25 / 27 » Model Checking Timed Automata with One or Two Clocks |
QEST
2005
IEEE
14 years 1 months ago
2005
IEEE
iLTL is a probabilistic temporal logic that can specify properties of multiple discrete time Markov chains (DTMCs). In this paper, we describe two related tools: MarkovEstimator a...
FPGA
2004
ACM
13 years 11 months ago
2004
ACM
Embedded systems combine a processor with dedicated logic to meet design specifications at a reasonable cost. The attempt to amalgamate two distinct design environments introduces...
TACAS
2010
Springer
13 years 5 months ago
2010
Springer
Systems and protocols combining concurrency and infinite state space occur quite often in practice, but are very difficult to verify automatically. At the same time, if the system ...
VLSID
2010
IEEE
13 years 5 months ago
2010
IEEE
Directed test generation is important for the functional verification of complex system-on-chip designs. SAT based bounded model checking is promising for counterexample generatio...
ISAAC
2009
Springer
14 years 2 months ago
2009
Springer
The problem of maintaining geometric structures for points in motion has been well studied over the years. Much theoretical work to date has been based on the assumption that point...