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DATE
1999
IEEE
14 years 1 months ago
1999
IEEE
In this paper, new and efficient BIST methodology and BIST hardware insertion algorithms are presented for RTL data paths obtained from high level synthesis. The methodology is ba...
AIIA
2007
Springer
14 years 3 months ago
2007
Springer
In this work, we present a constrained-based representation for specifying the goals of “course design”, that we call curricula model, and introduce a graphical language, groun...
ENTCS
2007
13 years 8 months ago
2007
The paper reports on the foundations and experimental results with a model checker for component connectors modelled by networks of channels in the calculus Reo. The specificatio...
SOFSEM
1997
Springer
14 years 28 days ago
1997
Springer
This paper surveys recent results in the area of virtual path layout in ATM networks. We present a model for the theoretical study of these layouts the model amounts to covering t...
ENTCS
2002
13 years 8 months ago
2002
or Abstraction in Model Checking Mar