Automated verification is a technique for establishing if certain properties, usually expressed in temporal logic, hold for a system model. The model can be defined using a high-l...
We show that recursive programs where variables range over finite domains can be effectively and efficiently analyzed by describing the analysis algorithm using a formula in a ...
Salvatore La Torre, Parthasarathy Madhusudan, Genn...
The Near-Horn Prolog procedures have been proposed as e ective procedures in the area of disjunctive logic programming, an extension of logic programming to the ( rstorder) non-Ho...
We introduce streaming data string transducers that map input data strings to output data strings in a single left-to-right pass in linear time. Data strings are (unbounded) seque...
We present a formal verification methodology that we have used on a computer system design project. The methodology integrates a temporal logic model checker with a conventional pr...