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» Model Classifications and Automated Verification
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DAC
2005
ACM
14 years 8 months ago
Simulation models for side-channel information leaks
Small, embedded integrated circuits (ICs) such as smart cards are vulnerable to so-called side-channel attacks (SCAs). The attacker can gain information by monitoring the power co...
Kris Tiri, Ingrid Verbauwhede
ANSS
2006
IEEE
14 years 1 months ago
An Integrative Modelling Approach for Simulation and Analysis of Adaptive Agents
To simulate adaptive agents with abilities matching those of their real-world counterparts, a natural approach is to incorporate adaptation mechanisms such as classical conditioni...
Tibor Bosse, Catholijn M. Jonker, Jan Treur
CADE
2007
Springer
14 years 8 months ago
Combination Methods for Satisfiability and Model-Checking of Infinite-State Systems
Manna and Pnueli have extensively shown how a mixture of first-order logic (FOL) and discrete Linear time Temporal Logic (LTL) is sufficient to precisely state verification problem...
Silvio Ghilardi, Enrica Nicolini, Silvio Ranise, D...
DAC
2004
ACM
14 years 8 months ago
Refining the SAT decision ordering for bounded model checking
Bounded Model Checking (BMC) relies on solving a sequence of highly correlated Boolean satisfiability (SAT) problems, each of which corresponds to the existence of counter-example...
Chao Wang, HoonSang Jin, Gary D. Hachtel, Fabio So...
DAC
2005
ACM
14 years 8 months ago
Minimising buffer requirements of synchronous dataflow graphs with model checking
Signal processing and multimedia applications are often implemented on resource constrained embedded systems. It is therefore important to find implementations that use as little ...
Marc Geilen, Twan Basten, Sander Stuijk