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» Model checking transactional memories
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DATE
2004
IEEE
130views Hardware» more  DATE 2004»
14 years 14 days ago
Utilizing Formal Assertions for System Design of Network Processors
System level modeling with executable languages such as C/C++ has been crucial in the development of large electronic systems from general processors to application specific desig...
Xi Chen, Yan Luo, Harry Hsieh, Laxmi N. Bhuyan, Fe...
HASKELL
2009
ACM
14 years 3 months ago
A compositional theory for STM Haskell
We address the problem of reasoning about Haskell programs that use Software Transactional Memory (STM). As a motivating example, we consider Haskell code for a concurrent non-det...
Johannes Borgström, Karthikeyan Bhargavan, An...
ICASSP
2011
IEEE
13 years 14 days ago
A methodology based on Transportation problem modeling for designing parallel interleaver architectures
For high-data-rate applications, turbo-like iterative decoders are implemented with parallel hardware architecture. However, to achieve high throughput, concurrent accesses to each...
Awais Sani, Philippe Coussy, Cyrille Chavet, Eric ...
SPAA
2005
ACM
14 years 2 months ago
Efficient algorithms for verifying memory consistency
One approach in verifying the correctness of a multiprocessor system is to show that its execution results comply with the memory consistency model it is meant to implement. It ha...
Chaiyasit Manovit, Sudheendra Hangal
PVLDB
2010
147views more  PVLDB 2010»
13 years 7 months ago
HYRISE - A Main Memory Hybrid Storage Engine
In this paper, we describe a main memory hybrid database system called HYRISE, which automatically partitions tables into vertical partitions of varying widths depending on how th...
Martin Grund, Jens Krüger, Hasso Plattner, Al...