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» Model checking transactional memories
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LCTRTS
2010
Springer
14 years 4 months ago
Design exploration and automatic generation of MPSoC platform TLMs from Kahn Process Network applications
With increasingly more complex Multi-Processor Systems on Chip (MPSoC) and shortening time-to- market projections, Transaction Level Modeling and Platform Aware Design are seen as...
Ines Viskic, Lochi Lo Chi Yu Lo, Daniel Gajski
ENTCS
2008
132views more  ENTCS 2008»
13 years 10 months ago
Distributed Verification of Multi-threaded C++ Programs
Verification of multi-threaded C++ programs poses three major challenges: the large number of states, states with huge sizes, and time intensive expansions of states. This paper p...
Stefan Edelkamp, Shahid Jabbar, Damian Sulewski
CORR
2011
Springer
124views Education» more  CORR 2011»
13 years 4 months ago
Parallel Recursive State Compression for Free
This paper focuses on reducing memory usage in enumerative model checking, while maintaining the multi-core scalability obtained in earlier work. We present a multi-core tree-based...
Alfons Laarman, Jaco van de Pol, Michael Weber 000...
ASPLOS
2008
ACM
13 years 12 months ago
Learning from mistakes: a comprehensive study on real world concurrency bug characteristics
The reality of multi-core hardware has made concurrent programs pervasive. Unfortunately, writing correct concurrent programs is difficult. Addressing this challenge requires adva...
Shan Lu, Soyeon Park, Eunsoo Seo, Yuanyuan Zhou
VLSID
2003
IEEE
180views VLSI» more  VLSID 2003»
14 years 10 months ago
Automating Formal Modular Verification of Asynchronous Real-Time Embedded Systems
Most verification tools and methodologies such as model checking, equivalence checking, hardware verification, software verification, and hardware-software coverification often fl...
Pao-Ann Hsiung, Shu-Yu Cheng