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» Model checking transactional memories
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RECOSOC
2007
116views Hardware» more  RECOSOC 2007»
13 years 9 months ago
IBC-EI: An Instruction Based Compression method with Encryption and Integrity Checking
Code Compression has been shown to be efficient in minimizing the memory requirements for embedded systems as well as in power consumption reduction and performance improvement. I...
Eduardo Wanderley Netto, Reouven Elbaz, Lionel Tor...
MICRO
2010
IEEE
202views Hardware» more  MICRO 2010»
13 years 2 months ago
Hardware Support for Relaxed Concurrency Control in Transactional Memory
Today's transactional memory systems implement the two-phase-locking (2PL) algorithm which aborts transactions every time a conflict happens. 2PL is a simple algorithm that pr...
Utku Aydonat, Tarek S. Abdelrahman
ISCA
2005
IEEE
101views Hardware» more  ISCA 2005»
14 years 1 months ago
Virtualizing Transactional Memory
Writing concurrent programs is difficult because of the complexity of ensuring proper synchronization. Conventional lock-based synchronization suffers from wellknown limitations, ...
Ravi Rajwar, Maurice Herlihy, Konrad K. Lai
SBACPAD
2008
IEEE
170views Hardware» more  SBACPAD 2008»
14 years 1 months ago
Using Analytical Models to Efficiently Explore Hardware Transactional Memory and Multi-Core Co-Design
Transactional memory is emerging as a parallel programming paradigm for multi-core processors. Despite the recent interest in transactional memory, there has been no study to char...
James Poe, Chang-Burm Cho, Tao Li
ACMMSP
2006
ACM
257views Hardware» more  ACMMSP 2006»
14 years 1 months ago
Memory models for open-nested transactions
Open nesting provides a loophole in the strict model of atomic transactions. Moss and Hosking suggested adapting open nesting for transactional memory, and Moss and a group at Sta...
Kunal Agrawal, Charles E. Leiserson, Jim Sukha