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ICST
2010
IEEE
13 years 6 months ago
Timed Moore Automata: Test Data Generation and Model Checking
Abstract—In this paper we introduce Timed Moore Automata, a specification formalism which is used in industrial train control applications for specifying the real-time behavior ...
Helge Löding, Jan Peleska
ASPDAC
2007
ACM
158views Hardware» more  ASPDAC 2007»
13 years 11 months ago
Symbolic Model Checking of Analog/Mixed-Signal Circuits
This paper presents a Boolean based symbolic model checking algorithm for the verification of analog/mixedsignal (AMS) circuits. The systems are modeled in VHDL-AMS, a hardware des...
David Walter, Scott Little, Nicholas Seegmiller, C...
SPIN
2009
Springer
14 years 2 months ago
Tool Presentation: Teaching Concurrency and Model Checking
This paper describes a set of software tools developed for teaching concurrency and model checking. jSpin is an elementary development environment for Spin that formats and filter...
Mordechai Ben-Ari
FORMATS
2007
Springer
14 years 1 months ago
Hypervolume Approximation in Timed Automata Model Checking
Dierence Bound Matrices (DBMs) are the most commonly used data structure for model checking timed automata. Since long they are being used in successful tools like Kronos or UPPAA...
Víctor A. Braberman, Jorge Lucángeli...
FMOODS
2007
13 years 9 months ago
Model Checking of Extended OCL Constraints on UML Models in SOCLe
We present the first tool that offers dynamic verification of extended traints on UML models. It translates a UML model into an Abstract State (ASM) which is transformed by an AS...
John Mullins, Raveca Oarga